CPU: vendor_id = "GenuineIntel" version information (1/eax): processor type = primary processor (0) family = 0x6 (6) model = 0xc (12) stepping id = 0x1 (1) extended family = 0x0 (0) extended model = 0x8 (8) (family synth) = 0x6 (6) (model synth) = 0x8c (140) (simple synth) = Intel (unknown type) (Tiger Lake-U B0) [Willow Cove] {Sunny Cove}, 10nm++ miscellaneous (1/ebx): process local APIC physical ID = 0x6 (6) maximum IDs for CPUs in pkg = 0x10 (16) CLFLUSH line size = 0x8 (8) brand index = 0x0 (0) brand id = 0x00 (0): unknown feature information (1/edx): x87 FPU on chip = true VME: virtual-8086 mode enhancement = true DE: debugging extensions = true PSE: page size extensions = true TSC: time stamp counter = true RDMSR and WRMSR support = true PAE: physical address extensions = true MCE: machine check exception = true CMPXCHG8B inst. = true APIC on chip = true SYSENTER and SYSEXIT = true MTRR: memory type range registers = true PTE global bit = true MCA: machine check architecture = true CMOV: conditional move/compare instr = true PAT: page attribute table = true PSE-36: page size extension = true PSN: processor serial number = ... CLFLUSH instruction = true DS: debug store = true ACPI: thermal monitor and clock ctrl = true MMX Technology = true FXSAVE/FXRSTOR = true SSE extensions = true SSE2 extensions = true SS: self snoop = true hyper-threading / multi-core supported = true TM: therm. monitor = true IA64 = false PBE: pending break event = true feature information (1/ecx): PNI/SSE3: Prescott New Instructions = true PCLMULDQ instruction = true DTES64: 64-bit debug store = true MONITOR/MWAIT = true CPL-qualified debug store = true VMX: virtual machine extensions = true SMX: safer mode extensions = false Enhanced Intel SpeedStep Technology = true TM2: thermal monitor 2 = true SSSE3 extensions = true context ID: adaptive or shared L1 data = false SDBG: IA32_DEBUG_INTERFACE = true FMA instruction = true CMPXCHG16B instruction = true xTPR disable = true PDCM: perfmon and debug = true PCID: process context identifiers = true DCA: direct cache access = false SSE4.1 extensions = true SSE4.2 extensions = true x2APIC: extended xAPIC support = true MOVBE instruction = true POPCNT instruction = true time stamp counter deadline = true AES instruction = true XSAVE/XSTOR states = true OS-enabled XSAVE/XSTOR = true AVX: advanced vector extensions = true F16C half-precision convert instruction = true RDRAND instruction = true hypervisor guest status = false cache and TLB information (2): 0xff: cache data is in CPUID leaf 4 0xfe: TLB data is in CPUID leaf 0x18 0xf0: 64 byte prefetching processor serial number = ... deterministic cache parameters (4): --- cache 0 --- cache type = data cache (1) cache level = 0x1 (1) self-initializing cache level = true fully associative cache = false maximum IDs for CPUs sharing cache = 0x1 (1) maximum IDs for cores in pkg = 0x7 (7) system coherency line size = 0x40 (64) physical line partitions = 0x1 (1) ways of associativity = 0xc (12) number of sets = 0x40 (64) WBINVD/INVD acts on lower caches = false inclusive to lower caches = false complex cache indexing = false number of sets (s) = 64 (size synth) = 49152 (48 KB) --- cache 1 --- cache type = instruction cache (2) cache level = 0x1 (1) self-initializing cache level = true fully associative cache = false maximum IDs for CPUs sharing cache = 0x1 (1) maximum IDs for cores in pkg = 0x7 (7) system coherency line size = 0x40 (64) physical line partitions = 0x1 (1) ways of associativity = 0x8 (8) number of sets = 0x40 (64) WBINVD/INVD acts on lower caches = false inclusive to lower caches = false complex cache indexing = false number of sets (s) = 64 (size synth) = 32768 (32 KB) --- cache 2 --- cache type = unified cache (3) cache level = 0x2 (2) self-initializing cache level = true fully associative cache = false maximum IDs for CPUs sharing cache = 0x1 (1) maximum IDs for cores in pkg = 0x7 (7) system coherency line size = 0x40 (64) physical line partitions = 0x1 (1) ways of associativity = 0x14 (20) number of sets = 0x400 (1024) WBINVD/INVD acts on lower caches = false inclusive to lower caches = false complex cache indexing = false number of sets (s) = 1024 (size synth) = 1310720 (1.2 MB) --- cache 3 --- cache type = unified cache (3) cache level = 0x3 (3) self-initializing cache level = true fully associative cache = false maximum IDs for CPUs sharing cache = 0xf (15) maximum IDs for cores in pkg = 0x7 (7) system coherency line size = 0x40 (64) physical line partitions = 0x1 (1) ways of associativity = 0x8 (8) number of sets = 0x4000 (16384) WBINVD/INVD acts on lower caches = false inclusive to lower caches = false complex cache indexing = true number of sets (s) = 16384 (size synth) = 8388608 (8 MB) --- cache 4 --- cache type = no more caches (0) MONITOR/MWAIT (5): smallest monitor-line size (bytes) = 0x40 (64) largest monitor-line size (bytes) = 0x40 (64) enum of Monitor-MWAIT exts supported = true supports intrs as break-event for MWAIT = true number of C0 sub C-states using MWAIT = 0x0 (0) number of C1 sub C-states using MWAIT = 0x2 (2) number of C2 sub C-states using MWAIT = 0x0 (0) number of C3 sub C-states using MWAIT = 0x1 (1) number of C4 sub C-states using MWAIT = 0x2 (2) number of C5 sub C-states using MWAIT = 0x1 (1) number of C6 sub C-states using MWAIT = 0x1 (1) number of C7 sub C-states using MWAIT = 0x1 (1) Thermal and Power Management Features (6): digital thermometer = true Intel Turbo Boost Technology = true ARAT always running APIC timer = true PLN power limit notification = true ECMD extended clock modulation duty = true PTM package thermal management = true HWP base registers = true HWP notification = true HWP activity window = true HWP energy performance preference = true HWP package level request = true HDC base registers = true Intel Turbo Boost Max Technology 3.0 = true HWP capabilities = true HWP PECI override = true flexible HWP = true IA32_HWP_REQUEST MSR fast access mode = true HW_FEEDBACK MSRs supported = false ignoring idle logical processor HWP req = true Thread Director = false digital thermometer thresholds = 0x2 (2) hardware coordination feedback = true ACNT2 available = false performance-energy bias capability = true number of enh hardware feedback classes = 0x0 (0) performance capability reporting = false energy efficiency capability reporting = false size of feedback struct (4KB pages) = 0x1 (1) index of CPU's row in feedback struct = 0x0 (0) extended feature flags (7): FSGSBASE instructions = true IA32_TSC_ADJUST MSR supported = true SGX: Software Guard Extensions supported = false BMI1 instructions = true HLE hardware lock elision = false AVX2: advanced vector extensions 2 = true FDP_EXCPTN_ONLY = true SMEP supervisor mode exec protection = true BMI2 instructions = true enhanced REP MOVSB/STOSB = true INVPCID instruction = true RTM: restricted transactional memory = false RDT-CMT/PQoS cache monitoring = false deprecated FPU CS/DS = true MPX: intel memory protection extensions = false RDT-CAT/PQE cache allocation = true AVX512F: AVX-512 foundation instructions = true AVX512DQ: double & quadword instructions = true RDSEED instruction = true ADX instructions = true SMAP: supervisor mode access prevention = true AVX512IFMA: integer fused multiply add = true PCOMMIT instruction = false CLFLUSHOPT instruction = true CLWB instruction = true Intel processor trace = true AVX512PF: prefetch instructions = false AVX512ER: exponent & reciprocal instrs = false AVX512CD: conflict detection instrs = true SHA instructions = true AVX512BW: byte & word instructions = true AVX512VL: vector length = true PREFETCHWT1 = false AVX512VBMI: vector byte manipulation = true UMIP: user-mode instruction prevention = true PKU protection keys for user-mode = true OSPKE CR4.PKE and RDPKRU/WRPKRU = true WAITPKG instructions = false AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = true CET_SS: CET shadow stack = true GFNI: Galois Field New Instructions = true VAES instructions = true VPCLMULQDQ instruction = true AVX512_VNNI: neural network instructions = true AVX512_BITALG: bit count/shiffle = true TME: Total Memory Encryption = false AVX512: VPOPCNTDQ instruction = true LA57: 57-bit addrs & 5-level paging = false BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0) RDPID: read processor ID supported = true KL: key locker = true bus lock detection = false CLDEMOTE supports cache line demote = false MOVDIRI instruction = true MOVDIR64B instruction = true ENQCMD instruction = false SGX_LC: SGX launch config supported = false PKS: supervisor protection keys = false AVX512_4VNNIW: neural network instrs = false AVX512_4FMAPS: multiply acc single prec = false fast short REP MOV = true UINTR: user interrupts = false AVX512_VP2INTERSECT: intersect mask regs = true SRBDS mitigation MSR available = true VERW MD_CLEAR microcode support = true RTM transaction always aborts = false TSX_FORCE_ABORT = false SERIALIZE instruction = false hybrid part = false TSXLDTRK: TSX suspend load addr tracking = false PCONFIG instruction = false LBR: architectural last branch records = false CET_IBT: CET indirect branch tracking = true AMX-BF16: tile bfloat16 support = false AVX512_FP16: fp16 support = false AMX-TILE: tile architecture support = false AMX-INT8: tile 8-bit integer support = false IBRS/IBPB: indirect branch restrictions = true STIBP: 1 thr indirect branch predictor = true L1D_FLUSH: IA32_FLUSH_CMD MSR = true IA32_ARCH_CAPABILITIES MSR = true IA32_CORE_CAPABILITIES MSR = true SSBD: speculative store bypass disable = true RAO-INT atomic instructions = false AVX-VNNI: AVX VNNI neural network instrs = false AVX512_BF16: bfloat16 instructions = false CMPccXADD instructions = false ArchPerfmonExt is valid = false fast zero-length MOVSB = false fast short STOSB = false fast short CMPSB, SCASB = false WRMSRNS instruction = false AMX-FP16: FP16 tile operations = false HRESET: history reset support = false AVX-IFMA: integer fused multiply add = false LAM: linear address masking = false RDMSRLIST, WRMSRLIST instructions = false IA32_PPIN & IA32_PPIN_CTL MSRs supported = false AVX-VNNI-INT8 instructions = false AVX-NE-CONVERT instructions = false PREFETCHIT0, PREFETCHIT1 instructions = false IPRED_CTRL: IBP disable = false RRSBA_CTRL: IBP bottomless RSB disable = false BHI_CTRL: IBP BHB-focused disable = false Direct Cache Access Parameters (9): PLATFORM_DCA_CAP MSR bits = 0 Architecture Performance Monitoring Features (0xa): version ID = 0x5 (5) number of counters per logical processor = 0x8 (8) bit width of counter = 0x30 (48) length of EBX bit vector = 0x8 (8) core cycle event = available instruction retired event = available reference cycles event = available last-level cache ref event = available last-level cache miss event = available branch inst retired event = available branch mispred retired event = available top-down slots event = available fixed counter 0 supported = true fixed counter 1 supported = true fixed counter 2 supported = true fixed counter 3 supported = true fixed counter 4 supported = false fixed counter 5 supported = false fixed counter 6 supported = false fixed counter 7 supported = false fixed counter 8 supported = false fixed counter 9 supported = false fixed counter 10 supported = false fixed counter 11 supported = false fixed counter 12 supported = false fixed counter 13 supported = false fixed counter 14 supported = false fixed counter 15 supported = false fixed counter 16 supported = false fixed counter 17 supported = false fixed counter 18 supported = false fixed counter 19 supported = false fixed counter 20 supported = false fixed counter 21 supported = false fixed counter 22 supported = false fixed counter 23 supported = false fixed counter 24 supported = false fixed counter 25 supported = false fixed counter 26 supported = false fixed counter 27 supported = false fixed counter 28 supported = false fixed counter 29 supported = false fixed counter 30 supported = false fixed counter 31 supported = false number of contiguous fixed counters = 0x4 (4) bit width of fixed counters = 0x30 (48) anythread deprecation = true x2APIC features / processor topology (0xb): extended APIC ID = 6 --- level 0 --- level number = 0x0 (0) level type = thread (1) bit width of level = 0x1 (1) number of logical processors at level = 0x2 (2) --- level 1 --- level number = 0x1 (1) level type = core (2) bit width of level = 0x4 (4) number of logical processors at level = 0x8 (8) --- level 2 --- level number = 0x2 (2) level type = invalid (0) bit width of level = 0x0 (0) number of logical processors at level = 0x0 (0) XSAVE features (0xd/0): XCR0 valid bit field mask = 0x00000000000002e7 XCR0 supported: x87 state = true XCR0 supported: SSE state = true XCR0 supported: AVX state = true XCR0 supported: MPX BNDREGS = false XCR0 supported: MPX BNDCSR = false XCR0 supported: AVX-512 opmask = true XCR0 supported: AVX-512 ZMM_Hi256 = true XCR0 supported: AVX-512 Hi16_ZMM = true IA32_XSS supported: PT state = false XCR0 supported: PKRU state = true XCR0 supported: CET_U state = false XCR0 supported: CET_S state = false IA32_XSS supported: HDC state = false IA32_XSS supported: UINTR state = false LBR supported = false IA32_XSS supported: HWP state = false XTILECFG supported = false XTILEDATA supported = false bytes required by fields in XCR0 = 0x00000a88 (2696) bytes required by XSAVE/XRSTOR area = 0x00000a88 (2696) XSAVE features (0xd/1): XSAVEOPT instruction = true XSAVEC instruction = true XGETBV instruction = true XSAVES/XRSTORS instructions = true XFD: extended feature disable supported = false SAVE area size in bytes = 0x00000998 (2456) IA32_XSS lower 32 bits valid bit field mask = 0x00003900 IA32_XSS upper 32 bits valid bit field mask = 0x00000000 AVX/YMM features (0xd/2): AVX/YMM save state byte size = 0x00000100 (256) AVX/YMM save state byte offset = 0x00000240 (576) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false XFD faulting supported = false AVX-512 opmask features (0xd/5): AVX-512 opmask save state byte size = 0x00000040 (64) AVX-512 opmask save state byte offset = 0x00000440 (1088) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false XFD faulting supported = false AVX-512 ZMM_Hi256 features (0xd/6): AVX-512 ZMM_Hi256 save state byte size = 0x00000200 (512) AVX-512 ZMM_Hi256 save state byte offset = 0x00000480 (1152) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false XFD faulting supported = false AVX-512 Hi16_ZMM features (0xd/7): AVX-512 Hi16_ZMM save state byte size = 0x00000400 (1024) AVX-512 Hi16_ZMM save state byte offset = 0x00000680 (1664) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false XFD faulting supported = false PT features (0xd/8): PT save state byte size = 0x00000080 (128) PT save state byte offset = 0x00000000 (0) supported in IA32_XSS or XCR0 = IA32_XSS (supervisor state) 64-byte alignment in compacted XSAVE = false XFD faulting supported = false PKRU features (0xd/9): PKRU save state byte size = 0x00000008 (8) PKRU save state byte offset = 0x00000a80 (2688) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false XFD faulting supported = false CET_U state features (0xd/0xb): CET_U state save state byte size = 0x00000010 (16) CET_U state save state byte offset = 0x00000000 (0) supported in IA32_XSS or XCR0 = IA32_XSS (supervisor state) 64-byte alignment in compacted XSAVE = false XFD faulting supported = false CET_S state features (0xd/0xc): CET_S state save state byte size = 0x00000018 (24) CET_S state save state byte offset = 0x00000000 (0) supported in IA32_XSS or XCR0 = IA32_XSS (supervisor state) 64-byte alignment in compacted XSAVE = false XFD faulting supported = false HDC features (0xd/0xd): HDC save state byte size = 0x00000008 (8) HDC save state byte offset = 0x00000000 (0) supported in IA32_XSS or XCR0 = IA32_XSS (supervisor state) 64-byte alignment in compacted XSAVE = false XFD faulting supported = false Quality of Service Monitoring Resource Type (0xf/0): Maximum range of RMID = 0 supports L3 cache QoS monitoring = false Resource Director Technology Allocation (0x10/0): L3 cache allocation technology supported = false L2 cache allocation technology supported = true memory bandwidth allocation supported = false L2 Cache Allocation Technology (0x10/2): length of capacity bit mask = 0x14 (20) Bit-granular map of isolation/contention = 0x00000000 infrequent updates of COS = false code and data prioritization supported = true highest COS number supported = 0x7 (7) 0x00000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000 Software Guard Extensions (SGX) capability (0x12/0): SGX1 supported = false SGX2 supported = false SGX ENCLV E*VIRTCHILD, ESETCONTEXT = false SGX ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC = false SGX ENCLU EVERIFYREPORT2 = false SGX ENCLU EDECCSSA = false MISCSELECT.EXINFO supported: #PF & #GP = false MISCSELECT.CPINFO supported: #CP = false MaxEnclaveSize_Not64 (log2) = 0x0 (0) MaxEnclaveSize_64 (log2) = 0x0 (0) SGX attributes: ECREATE SECS.ATTRIBUTES (0x12/1): valid bit mask = 0x00000000000000000000000000000000 enclave initialized by EINIT = false enclave debugger read/write permission = false enclave 64-bit mode = false provisioning key available = false EINIT token key available = false CET attributes enabled = false KSS key separation & sharing enabled = false XFRM: XSAVE feature request mask = 0x0000000000000000 XCR0 supported: x87 state = false XCR0 supported: SSE state = false XCR0 supported: AVX state = false XCR0 supported: MPX BNDREGS = false XCR0 supported: MPX BNDCSR = false XCR0 supported: AVX-512 opmask = false XCR0 supported: AVX-512 ZMM_Hi256 = false XCR0 supported: AVX-512 Hi16_ZMM = false IA32_XSS supported: PT state = false XCR0 supported: PKRU state = false XCR0 supported: CET_U state = false XCR0 supported: CET_S state = false IA32_XSS supported: HDC state = false IA32_XSS supported: UINTR state = false LBR supported = false IA32_XSS supported: HWP state = false XTILECFG supported = false XTILEDATA supported = false SGX Enclave Page Cache (EPC) enumeration (0x12/0x2): type = invalid 0x00000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000 Intel Processor Trace (0x14): IA32_RTIT_CR3_MATCH is accessible = true configurable PSB & cycle-accurate = true IP & TraceStop filtering; PT preserve = true MTC timing packet; suppress COFI-based = true PTWRITE support = false power event trace support = false PSB/PMI preservation support = true IA32_RTIT_CTL EventEn enable supported = false IA32_RTIT_CTL DisTNT disable supported = false ToPA output scheme support = true ToPA can hold many output entries = true single-range output scheme support = true output to trace transport = false IP payloads have LIP values & CS = false configurable address ranges = 0x2 (2) supported MTC periods bitmask = 0x249 (585) supported cycle threshold bitmask = 0x1fff (8191) supported config PSB freq bitmask = 0x3f (63) Time Stamp Counter/Core Crystal Clock Information (0x15): TSC/clock ratio = 126/2 nominal core crystal clock = 38400000 Hz Processor Frequency Information (0x16): Core Base Frequency (MHz) = 0x960 (2400) Core Maximum Frequency (MHz) = 0x1068 (4200) Bus (Reference) Frequency (MHz) = 0x64 (100) System-On-Chip Vendor Attribute (0x17/0): vendor id = 0x0 (0) vendor scheme = assigned by intel project id = 0x00000000 (0) stepping id = 0x00000000 (0) Deterministic Address Translation Parameters (0x18/0): 4KB page size entries supported = false 2MB page size entries supported = false 4MB page size entries supported = false 1GB page size entries supported = false partitioning = soft between logical processors ways of associativity = 0x0 (0) number of sets = 0x00000000 (0) translation cache type = invalid (0) translation cache level = 0x1 (1) fully associative = false maximum number of addressible IDs = 0x0 (0) Deterministic Address Translation Parameters (0x18/1): 4KB page size entries supported = true 2MB page size entries supported = false 4MB page size entries supported = false 1GB page size entries supported = false partitioning = soft between logical processors ways of associativity = 0x8 (8) number of sets = 0x00000010 (16) translation cache type = instruction TLB translation cache level = 0x2 (2) fully associative = false maximum number of addressible IDs = 0x1 (1) Deterministic Address Translation Parameters (0x18/2): 4KB page size entries supported = false 2MB page size entries supported = true 4MB page size entries supported = true 1GB page size entries supported = false partitioning = soft between logical processors ways of associativity = 0x8 (8) number of sets = 0x00000002 (2) translation cache type = instruction TLB translation cache level = 0x2 (2) fully associative = false maximum number of addressible IDs = 0x1 (1) Deterministic Address Translation Parameters (0x18/3): 4KB page size entries supported = true 2MB page size entries supported = true 4MB page size entries supported = true 1GB page size entries supported = true partitioning = soft between logical processors ways of associativity = 0x10 (16) number of sets = 0x00000001 (1) translation cache type = store-only TLB translation cache level = 0x2 (2) fully associative = true maximum number of addressible IDs = 0x1 (1) Deterministic Address Translation Parameters (0x18/4): 4KB page size entries supported = true 2MB page size entries supported = false 4MB page size entries supported = false 1GB page size entries supported = false partitioning = soft between logical processors ways of associativity = 0x4 (4) number of sets = 0x00000010 (16) translation cache type = load-only TLB translation cache level = 0x2 (2) fully associative = false maximum number of addressible IDs = 0x1 (1) Deterministic Address Translation Parameters (0x18/5): 4KB page size entries supported = false 2MB page size entries supported = true 4MB page size entries supported = true 1GB page size entries supported = false partitioning = soft between logical processors ways of associativity = 0x4 (4) number of sets = 0x00000008 (8) translation cache type = load-only TLB translation cache level = 0x2 (2) fully associative = false maximum number of addressible IDs = 0x1 (1) Deterministic Address Translation Parameters (0x18/6): 4KB page size entries supported = false 2MB page size entries supported = false 4MB page size entries supported = false 1GB page size entries supported = true partitioning = soft between logical processors ways of associativity = 0x8 (8) number of sets = 0x00000001 (1) translation cache type = load-only TLB translation cache level = 0x2 (2) fully associative = true maximum number of addressible IDs = 0x1 (1) Deterministic Address Translation Parameters (0x18/7): 4KB page size entries supported = true 2MB page size entries supported = true 4MB page size entries supported = true 1GB page size entries supported = false partitioning = soft between logical processors ways of associativity = 0x8 (8) number of sets = 0x00000080 (128) translation cache type = unified TLB translation cache level = 0x3 (3) fully associative = false maximum number of addressible IDs = 0x1 (1) Deterministic Address Translation Parameters (0x18/8): 4KB page size entries supported = true 2MB page size entries supported = false 4MB page size entries supported = false 1GB page size entries supported = true partitioning = soft between logical processors ways of associativity = 0x8 (8) number of sets = 0x00000080 (128) translation cache type = unified TLB translation cache level = 0x3 (3) fully associative = false maximum number of addressible IDs = 0x1 (1) Key Locker information (0x19): CPL0-only restriction supported = true no-encrypt restriction supported = true no-decrypt restriction supported = true AESKLE: AES instructions = false AES wide instructions = true MSRs & IWKEY backups = true LOADIWKEY NoBackup parameter = true IWKEY randomization supported = true Hybrid Information (0x1a/0): native model ID of core = 0x0 (0) core type = 0x0 (0) PCONFIG information (0x1b/0x0): sub-leaf type = invalid (0) PCONFIG information (0x1b/0x1): sub-leaf type = invalid (0) extended feature flags (0x80000001/edx): SYSCALL and SYSRET instructions = true execution disable = true 1-GB large page support = true RDTSCP = true 64-bit extensions technology available = true Intel feature flags (0x80000001/ecx): LAHF/SAHF supported in 64-bit mode = true LZCNT advanced bit manipulation = true 3DNow! PREFETCH/PREFETCHW instructions = true brand = "11th Gen Intel(R) Core(TM) i5-1135G7 @ 2.40GHz" L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax): instruction # entries = 0x0 (0) instruction associativity = 0x0 (0) data # entries = 0x0 (0) data associativity = 0x0 (0) L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx): instruction # entries = 0x0 (0) instruction associativity = 0x0 (0) data # entries = 0x0 (0) data associativity = 0x0 (0) L1 data cache information (0x80000005/ecx): line size (bytes) = 0x0 (0) lines per tag = 0x0 (0) associativity = 0x0 (0) size (KB) = 0x0 (0) L1 instruction cache information (0x80000005/edx): line size (bytes) = 0x0 (0) lines per tag = 0x0 (0) associativity = 0x0 (0) size (KB) = 0x0 (0) L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax): instruction # entries = 0x0 (0) instruction associativity = L2 off (0) data # entries = 0x0 (0) data associativity = L2 off (0) L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx): instruction # entries = 0x0 (0) instruction associativity = L2 off (0) data # entries = 0x0 (0) data associativity = L2 off (0) L2 unified cache information (0x80000006/ecx): line size (bytes) = 0x40 (64) lines per tag = 0x0 (0) associativity = 0x7 (7) size (KB) = 0x100 (256) L3 cache information (0x80000006/edx): line size (bytes) = 0x0 (0) lines per tag = 0x0 (0) associativity = L2 off (0) size (in 512KB units) = 0x0 (0) RAS Capability (0x80000007/ebx): MCA overflow recovery support = false SUCCOR support = false HWA: hardware assert support = false scalable MCA support = false Advanced Power Management Features (0x80000007/ecx): CmpUnitPwrSampleTimeRatio = 0x0 (0) Advanced Power Management Features (0x80000007/edx): TS: temperature sensing diode = false FID: frequency ID control = false VID: voltage ID control = false TTP: thermal trip = false TM: thermal monitor = false STC: software thermal control = false 100 MHz multiplier control = false hardware P-State control = false TscInvariant = true CPB: core performance boost = false read-only effective frequency interface = false processor feedback interface = false APM power reporting = false connected standby = false RAPL: running average power limit = false Physical Address and Linear Address Size (0x80000008/eax): maximum physical address bits = 0x27 (39) maximum linear (virtual) address bits = 0x30 (48) maximum guest physical address bits = 0x0 (0) Extended Feature Extensions ID (0x80000008/ebx): CLZERO instruction = false instructions retired count support = false always save/restore error pointers = false INVLPGB instruction = false RDPRU instruction = false memory bandwidth enforcement = false MCOMMIT instruction = false WBNOINVD instruction = false IBPB: indirect branch prediction barrier = false interruptible WBINVD, WBNOINVD = false IBRS: indirect branch restr speculation = false STIBP: 1 thr indirect branch predictor = false CPU prefers: IBRS always on = false CPU prefers: STIBP always on = false IBRS preferred over software solution = false IBRS provides same mode protection = false EFER[LMSLE] not supported = false INVLPGB supports TLB flush guest nested = false ppin processor id number supported = false SSBD: speculative store bypass disable = false virtualized SSBD = false SSBD fixed in hardware = false CPPC: collaborative processor perf ctrl = false PSFD: predictive store forward disable = false not vulnerable to branch type confusion = false branch sampling feature support = false (vuln to branch type confusion synth) = true Size Identifiers (0x80000008/ecx): number of CPU cores = 0x1 (1) ApicIdCoreIdSize = 0x0 (0) performance time-stamp counter size = 40 bits (0) Feature Extended Size (0x80000008/edx): max page count for INVLPGB instruction = 0x0 (0) RDPRU instruction max input support = 0x0 (0) (multi-processing synth) = multi-core (c=4), hyper-threaded (t=2) (multi-processing method) = Intel leaf 0xb (APIC widths synth): CORE_width=4 SMT_width=1 (APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=0 (uarch synth) = Intel Willow Cove {Sunny Cove}, 10nm++ (synth) = Intel Core i*-11000 / i*-1100G* (Tiger Lake-U B0) [Willow Cove] {Sunny Cove}, 10nm++