CPU: vendor_id = "AuthenticAMD" version information (1/eax): processor type = primary processor (0) family = 0xf (15) model = 0x3 (3) stepping id = 0x2 (2) extended family = 0x0 (0) extended model = 0x2 (2) (family synth) = 0xf (15) (model synth) = 0x23 (35) (simple synth) = AMD Athlon 64 (unknown type) (Toledo/Manchester/Denmark JH-E6) [K8], 939-pin, 90nm miscellaneous (1/ebx): process local APIC physical ID = 0x0 (0) maximum IDs for CPUs in pkg = 0x2 (2) CLFLUSH line size = 0x8 (8) brand index = 0x0 (0) brand id = 0x00 (0): unknown feature information (1/edx): x87 FPU on chip = true VME: virtual-8086 mode enhancement = true DE: debugging extensions = true PSE: page size extensions = true TSC: time stamp counter = true RDMSR and WRMSR support = true PAE: physical address extensions = true MCE: machine check exception = true CMPXCHG8B inst. = true APIC on chip = true SYSENTER and SYSEXIT = true MTRR: memory type range registers = true PTE global bit = true MCA: machine check architecture = true CMOV: conditional move/compare instr = true PAT: page attribute table = true PSE-36: page size extension = true PSN: processor serial number = ... CLFLUSH instruction = true DS: debug store = false ACPI: thermal monitor and clock ctrl = false MMX Technology = true FXSAVE/FXRSTOR = true SSE extensions = true SSE2 extensions = true SS: self snoop = false hyper-threading / multi-core supported = true TM: therm. monitor = false IA64 = false PBE: pending break event = false feature information (1/ecx): PNI/SSE3: Prescott New Instructions = true PCLMULDQ instruction = false DTES64: 64-bit debug store = false MONITOR/MWAIT = false CPL-qualified debug store = false VMX: virtual machine extensions = false SMX: safer mode extensions = false Enhanced Intel SpeedStep Technology = false TM2: thermal monitor 2 = false SSSE3 extensions = false context ID: adaptive or shared L1 data = false SDBG: IA32_DEBUG_INTERFACE = false FMA instruction = false CMPXCHG16B instruction = false xTPR disable = false PDCM: perfmon and debug = false PCID: process context identifiers = false DCA: direct cache access = false SSE4.1 extensions = false SSE4.2 extensions = false x2APIC: extended xAPIC support = false MOVBE instruction = false POPCNT instruction = false time stamp counter deadline = false AES instruction = false XSAVE/XSTOR states = false OS-enabled XSAVE/XSTOR = false AVX: advanced vector extensions = false F16C half-precision convert instruction = false RDRAND instruction = false hypervisor guest status = false extended processor signature (0x80000001/eax): family/generation = 0xf (15) model = 0x3 (3) stepping id = 0x2 (2) extended family = 0x0 (0) extended model = 0x2 (2) (family synth) = 0xf (15) (model synth) = 0x23 (35) (simple synth) = AMD Athlon 64 (unknown type) (Toledo/Manchester/Denmark JH-E6) [K8], 939-pin, 90nm extended feature flags (0x80000001/edx): x87 FPU on chip = true virtual-8086 mode enhancement = true debugging extensions = true page size extensions = true time stamp counter = true RDMSR and WRMSR support = true physical address extensions = true machine check exception = true CMPXCHG8B inst. = true APIC on chip = true SYSCALL and SYSRET instructions = true memory type range registers = true global paging extension = true machine check architecture = true conditional move/compare instruction = true page attribute table = true page size extension = true multiprocessing capable = false no-execute page protection = true AMD multimedia instruction extensions = true MMX Technology = true FXSAVE/FXRSTOR = true SSE extensions = true 1-GB large page support = false RDTSCP = false long mode (AA-64) = true 3DNow! instruction extensions = true 3DNow! instructions = true extended brand id (0x80000001/ebx): raw = 0x156 (342) BrandId = 0x156 (342) BrandTableIndex = 0x5 (5) NN = 0x56 (86) AMD feature flags (0x80000001/ecx): LAHF/SAHF supported in 64-bit mode = true CMP Legacy = true SVM: secure virtual machine = false extended APIC space = false AltMovCr8 = false LZCNT advanced bit manipulation = false SSE4A support = false misaligned SSE mode = false 3DNow! PREFETCH/PREFETCHW instructions = false OS visible workaround = false instruction based sampling = false XOP support = false SKINIT/STGI support = false watchdog timer support = false lightweight profiling support = false 4-operand FMA instruction = false TCE: translation cache extension = false NodeId MSR C001100C = false TBM support = false topology extensions = false core performance counter extensions = false NB/DF performance counter extensions = false data breakpoint extension = false performance time-stamp counter support = false LLC performance counter extensions = false MWAITX/MONITORX supported = false Address mask extension support = false brand = "AMD Athlon(tm) 64 X2 Dual Core Processor 4400+" L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax): instruction # entries = 0x8 (8) instruction associativity = 0xff (255) data # entries = 0x8 (8) data associativity = 0xff (255) L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx): instruction # entries = 0x20 (32) instruction associativity = 0xff (255) data # entries = 0x20 (32) data associativity = 0xff (255) L1 data cache information (0x80000005/ecx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 0x2 (2) size (KB) = 0x40 (64) L1 instruction cache information (0x80000005/edx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 0x2 (2) size (KB) = 0x40 (64) L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax): instruction # entries = 0x0 (0) instruction associativity = L2 off (0) data # entries = 0x0 (0) data associativity = L2 off (0) L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx): instruction # entries = 0x200 (512) instruction associativity = 4-way (4) data # entries = 0x200 (512) data associativity = 4-way (4) L2 unified cache information (0x80000006/ecx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 16-way (8) size (KB) = 0x400 (1024) L3 cache information (0x80000006/edx): line size (bytes) = 0x0 (0) lines per tag = 0x0 (0) associativity = L2 off (0) size (in 512KB units) = 0x0 (0) RAS Capability (0x80000007/ebx): MCA overflow recovery support = false SUCCOR support = false HWA: hardware assert support = false scalable MCA support = false Advanced Power Management Features (0x80000007/ecx): CmpUnitPwrSampleTimeRatio = 0x0 (0) Advanced Power Management Features (0x80000007/edx): TS: temperature sensing diode = true FID: frequency ID control = true VID: voltage ID control = true TTP: thermal trip = true TM: thermal monitor = false STC: software thermal control = false 100 MHz multiplier control = false hardware P-State control = false TscInvariant = false CPB: core performance boost = false read-only effective frequency interface = false processor feedback interface = false APM power reporting = false connected standby = false RAPL: running average power limit = false Physical Address and Linear Address Size (0x80000008/eax): maximum physical address bits = 0x28 (40) maximum linear (virtual) address bits = 0x30 (48) maximum guest physical address bits = 0x0 (0) Extended Feature Extensions ID (0x80000008/ebx): CLZERO instruction = false instructions retired count support = false always save/restore error pointers = false INVLPGB instruction = false RDPRU instruction = false memory bandwidth enforcement = false MCOMMIT instruction = false WBNOINVD instruction = false IBPB: indirect branch prediction barrier = false interruptible WBINVD, WBNOINVD = false IBRS: indirect branch restr speculation = false STIBP: 1 thr indirect branch predictor = false CPU prefers: IBRS always on = false CPU prefers: STIBP always on = false IBRS preferred over software solution = false IBRS provides same mode protection = false EFER[LMSLE] not supported = false INVLPGB supports TLB flush guest nested = false ppin processor id number supported = false SSBD: speculative store bypass disable = false virtualized SSBD = false SSBD fixed in hardware = false CPPC: collaborative processor perf ctrl = false PSFD: predictive store forward disable = false not vulnerable to branch type confusion = false branch sampling feature support = false (vuln to branch type confusion synth) = true Size Identifiers (0x80000008/ecx): number of CPU cores = 0x2 (2) ApicIdCoreIdSize = 0x0 (0) performance time-stamp counter size = 40 bits (0) Feature Extended Size (0x80000008/edx): max page count for INVLPGB instruction = 0x0 (0) RDPRU instruction max input support = 0x0 (0) SVM Secure Virtual Machine (0x8000000a/eax): SvmRev: SVM revision = 0x0 (0) SVM Secure Virtual Machine (0x8000000a/edx): nested paging = false LBR virtualization = false SVM lock = false NRIP save = false MSR based TSC rate control = false VMCB clean bits support = false flush by ASID = false decode assists = false SSSE3/SSE5 opcode set disable = false pause intercept filter = false pause filter threshold = false AVIC: AMD virtual interrupt controller = false virtualized VMLOAD/VMSAVE = false virtualized global interrupt flag (GIF) = false GMET: guest mode execute trap = false X2AVIC: virtualized X2APIC = false supervisor shadow stack = false guest Spec_ctl support = false host MCE override = false INVLPGB/TLBSYNC hyperv interc enable = false guest SVME addr check = false NASID: number of address space identifiers = 0x0 (0): (instruction supported synth): CMPXCHG8B = true conditional move/compare = true PREFETCH/PREFETCHW = true (multi-processing synth) = multi-core (c=2) (multi-processing method) = AMD (APIC widths synth): CORE_width=1 SMT_width=0 (APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0 (uarch synth) = AMD K8, 939-pin, 90nm (synth) = AMD Athlon 64 X2 (Toledo JH-E6) Processor 4400+ [K8], 939-pin, 90nm