CPU: vendor_id = "AuthenticAMD" version information (1/eax): processor type = primary processor (0) family = 0xf (15) model = 0x1 (1) stepping id = 0x2 (2) extended family = 0xa (10) extended model = 0x6 (6) (family synth) = 0x19 (25) (model synth) = 0x61 (97) (simple synth) = AMD Ryzen (Raphael B2) [Zen 4], 5nm miscellaneous (1/ebx): process local APIC physical ID = 0x1e (30) maximum IDs for CPUs in pkg = 0x20 (32) CLFLUSH line size = 0x8 (8) brand index = 0x0 (0) brand id = 0x00 (0): unknown feature information (1/edx): x87 FPU on chip = true VME: virtual-8086 mode enhancement = true DE: debugging extensions = true PSE: page size extensions = true TSC: time stamp counter = true RDMSR and WRMSR support = true PAE: physical address extensions = true MCE: machine check exception = true CMPXCHG8B inst. = true APIC on chip = true SYSENTER and SYSEXIT = true MTRR: memory type range registers = true PTE global bit = true MCA: machine check architecture = true CMOV: conditional move/compare instr = true PAT: page attribute table = true PSE-36: page size extension = true PSN: processor serial number = ... CLFLUSH instruction = true DS: debug store = false ACPI: thermal monitor and clock ctrl = false MMX Technology = true FXSAVE/FXRSTOR = true SSE extensions = true SSE2 extensions = true SS: self snoop = false hyper-threading / multi-core supported = true TM: therm. monitor = false IA64 = false PBE: pending break event = false feature information (1/ecx): PNI/SSE3: Prescott New Instructions = true PCLMULDQ instruction = true DTES64: 64-bit debug store = false MONITOR/MWAIT = true CPL-qualified debug store = false VMX: virtual machine extensions = false SMX: safer mode extensions = false Enhanced Intel SpeedStep Technology = false TM2: thermal monitor 2 = false SSSE3 extensions = true context ID: adaptive or shared L1 data = false SDBG: IA32_DEBUG_INTERFACE = false FMA instruction = true CMPXCHG16B instruction = true xTPR disable = false PDCM: perfmon and debug = false PCID: process context identifiers = false DCA: direct cache access = false SSE4.1 extensions = true SSE4.2 extensions = true x2APIC: extended xAPIC support = true MOVBE instruction = true POPCNT instruction = true time stamp counter deadline = false AES instruction = true XSAVE/XSTOR states = true OS-enabled XSAVE/XSTOR = true AVX: advanced vector extensions = true F16C half-precision convert instruction = true RDRAND instruction = true hypervisor guest status = false cache and TLB information (2): processor serial number = ... deterministic cache parameters (4): --- cache 0 --- cache type = no more caches (0) MONITOR/MWAIT (5): smallest monitor-line size (bytes) = 0x40 (64) largest monitor-line size (bytes) = 0x40 (64) enum of Monitor-MWAIT exts supported = true supports intrs as break-event for MWAIT = true number of C0 sub C-states using MWAIT = 0x1 (1) number of C1 sub C-states using MWAIT = 0x1 (1) number of C2 sub C-states using MWAIT = 0x0 (0) number of C3 sub C-states using MWAIT = 0x0 (0) number of C4 sub C-states using MWAIT = 0x0 (0) number of C5 sub C-states using MWAIT = 0x0 (0) number of C6 sub C-states using MWAIT = 0x0 (0) number of C7 sub C-states using MWAIT = 0x0 (0) Thermal and Power Management Features (6): digital thermometer = false Intel Turbo Boost Technology = false ARAT always running APIC timer = true PLN power limit notification = false ECMD extended clock modulation duty = false PTM package thermal management = false HWP base registers = false HWP notification = false HWP activity window = false HWP energy performance preference = false HWP package level request = false HDC base registers = false Intel Turbo Boost Max Technology 3.0 = false HWP capabilities = false HWP PECI override = false flexible HWP = false IA32_HWP_REQUEST MSR fast access mode = false HW_FEEDBACK MSRs supported = false ignoring idle logical processor HWP req = false Thread Director = false IA32_HW_FEEDBACK_THREAD_CONFIG bit 25 = false digital thermometer thresholds = 0x0 (0) hardware coordination feedback = true ACNT2 available = false performance-energy bias capability = false number of enh hardware feedback classes = 0x0 (0) performance capability reporting = false energy efficiency capability reporting = false size of feedback struct (4KB pages) = 0x1 (1) index of CPU's row in feedback struct = 0x0 (0) extended feature flags (7): FSGSBASE instructions = true IA32_TSC_ADJUST MSR supported = false SGX: Software Guard Extensions supported = false BMI1 instructions = true HLE hardware lock elision = false AVX2: advanced vector extensions 2 = true FDP_EXCPTN_ONLY = false SMEP supervisor mode exec protection = true BMI2 instructions = true enhanced REP MOVSB/STOSB = true INVPCID instruction = true RTM: restricted transactional memory = false RDT-CMT/PQoS cache monitoring = true deprecated FPU CS/DS = false MPX: intel memory protection extensions = false RDT-CAT/PQE cache allocation = true AVX512F: AVX-512 foundation instructions = true AVX512DQ: double & quadword instructions = true RDSEED instruction = true ADX instructions = true SMAP: supervisor mode access prevention = true AVX512IFMA: integer fused multiply add = true PCOMMIT instruction = false CLFLUSHOPT instruction = true CLWB instruction = true Intel processor trace = false AVX512PF: prefetch instructions = false AVX512ER: exponent & reciprocal instrs = false AVX512CD: conflict detection instrs = true SHA instructions = true AVX512BW: byte & word instructions = true AVX512VL: vector length = true PREFETCHWT1 = false AVX512VBMI: vector byte manipulation = true UMIP: user-mode instruction prevention = true PKU protection keys for user-mode = true OSPKE CR4.PKE and RDPKRU/WRPKRU = true WAITPKG instructions = false AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = true CET_SS: CET shadow stack = true GFNI: Galois Field New Instructions = true VAES instructions = true VPCLMULQDQ instruction = true AVX512_VNNI: neural network instructions = true AVX512_BITALG: bit count/shiffle = true TME: Total Memory Encryption = false AVX512: VPOPCNTDQ instruction = true LA57: 57-bit addrs & 5-level paging = false BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0) RDPID: read processor ID supported = true KL: key locker = false bus lock detection = false CLDEMOTE supports cache line demote = false MOVDIRI instruction = false MOVDIR64B instruction = false ENQCMD instruction = false SGX_LC: SGX launch config supported = false PKS: supervisor protection keys = false SGX-KEYS: SGX attestation services = false AVX512_4VNNIW: neural network instrs = false AVX512_4FMAPS: multiply acc single prec = false fast short REP MOV = true UINTR: user interrupts = false AVX512_VP2INTERSECT: intersect mask regs = false IA32_MCU_OPT_CTRL SRBDS mitigation MSR = false VERW MD_CLEAR microcode support = false RTM transaction always aborts = false IA32_TSX_FORCE_ABORT MSR = false SERIALIZE instruction = false hybrid part = false TSXLDTRK: TSX suspend load addr tracking = false PCONFIG instruction = false LBR: architectural last branch records = false CET_IBT: CET indirect branch tracking = false AMX-BF16: tile bfloat16 support = false AVX512_FP16: fp16 support = false AMX-TILE: tile architecture support = false AMX-INT8: tile 8-bit integer support = false IBRS/IBPB: indirect branch restrictions = false STIBP: 1 thr indirect branch predictor = false L1D_FLUSH: IA32_FLUSH_CMD MSR = true IA32_ARCH_CAPABILITIES MSR = false IA32_CORE_CAPABILITIES MSR = false SSBD: speculative store bypass disable = false RAO-INT atomic instructions = false AVX-VNNI: AVX VNNI neural network instrs = false AVX512_BF16: bfloat16 instructions = true LASS: linear address space separation = false CMPccXADD instructions = false ArchPerfmonExt is valid = false fast zero-length MOVSB = false fast short STOSB = false fast short CMPSB, SCASB = false WRMSRNS instruction = false AMX-FP16: FP16 tile operations = false HRESET: history reset support = false AVX-IFMA: integer fused multiply add = false LAM: linear address masking = false RDMSRLIST, WRMSRLIST instructions = false IA32_PPIN & IA32_PPIN_CTL MSRs supported = false AVX-VNNI-INT8 instructions = false AVX-NE-CONVERT instructions = false PREFETCHIT0, PREFETCHIT1 instructions = false CET_SSS: shadow stacks w/o page faults = false Direct Cache Access Parameters (9): PLATFORM_DCA_CAP MSR bits = 0 Architecture Performance Monitoring Features (0xa): version ID = 0x0 (0) number of counters per logical processor = 0x0 (0) bit width of counter = 0x0 (0) length of EBX bit vector = 0x0 (0) core cycle event = not available instruction retired event = not available reference cycles event = not available last-level cache ref event = not available last-level cache miss event = not available branch inst retired event = not available branch mispred retired event = not available top-down slots event = not available fixed counter 0 supported = false fixed counter 1 supported = false fixed counter 2 supported = false fixed counter 3 supported = false fixed counter 4 supported = false fixed counter 5 supported = false fixed counter 6 supported = false fixed counter 7 supported = false fixed counter 8 supported = false fixed counter 9 supported = false fixed counter 10 supported = false fixed counter 11 supported = false fixed counter 12 supported = false fixed counter 13 supported = false fixed counter 14 supported = false fixed counter 15 supported = false fixed counter 16 supported = false fixed counter 17 supported = false fixed counter 18 supported = false fixed counter 19 supported = false fixed counter 20 supported = false fixed counter 21 supported = false fixed counter 22 supported = false fixed counter 23 supported = false fixed counter 24 supported = false fixed counter 25 supported = false fixed counter 26 supported = false fixed counter 27 supported = false fixed counter 28 supported = false fixed counter 29 supported = false fixed counter 30 supported = false fixed counter 31 supported = false number of contiguous fixed counters = 0x0 (0) bit width of fixed counters = 0x0 (0) anythread deprecation = false x2APIC features / processor topology (0xb): extended APIC ID = 30 --- level 0 --- level number = 0x0 (0) level type = thread (1) bit width of level = 0x1 (1) number of logical processors at level = 0x2 (2) --- level 1 --- level number = 0x1 (1) level type = core (2) bit width of level = 0x5 (5) number of logical processors at level = 0x20 (32) --- level 2 --- level number = 0x2 (2) level type = invalid (0) bit width of level = 0x0 (0) number of logical processors at level = 0x0 (0) XSAVE features (0xd/0): XCR0 valid bit field mask = 0x00000000000002e7 x87 state = true SSE state = true AVX state = true MPX BNDREGS = false MPX BNDCSR = false AVX-512 opmask = true AVX-512 ZMM_Hi256 = true AVX-512 Hi16_ZMM = true PKRU state = true XTILECFG state = false XTILEDATA state = false bytes required by fields in XCR0 = 0x00000988 (2440) bytes required by XSAVE/XRSTOR area = 0x00000988 (2440) XSAVEOPT instruction = true XSAVEC instruction = true XGETBV instruction = true XSAVES/XRSTORS instructions = true XFD: extended feature disable supported = false SAVE area size in bytes = 0x00000988 (2440) IA32_XSS valid bit field mask = 0x0000000000001800 PT state = false PASID state = false CET_U user state = true CET_S supervisor state = true HDC state = false UINTR state = false LBR state = false HWP state = false AVX/YMM features (0xd/2): AVX/YMM save state byte size = 0x00000100 (256) AVX/YMM save state byte offset = 0x00000240 (576) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false XFD faulting supported = false AVX-512 opmask features (0xd/5): AVX-512 opmask save state byte size = 0x00000040 (64) AVX-512 opmask save state byte offset = 0x00000340 (832) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false XFD faulting supported = false AVX-512 ZMM_Hi256 features (0xd/6): AVX-512 ZMM_Hi256 save state byte size = 0x00000200 (512) AVX-512 ZMM_Hi256 save state byte offset = 0x00000380 (896) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false XFD faulting supported = false AVX-512 Hi16_ZMM features (0xd/7): AVX-512 Hi16_ZMM save state byte size = 0x00000400 (1024) AVX-512 Hi16_ZMM save state byte offset = 0x00000580 (1408) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false XFD faulting supported = false PKRU features (0xd/9): PKRU save state byte size = 0x00000008 (8) PKRU save state byte offset = 0x00000980 (2432) supported in IA32_XSS or XCR0 = XCR0 (user state) 64-byte alignment in compacted XSAVE = false XFD faulting supported = false CET_U user features (0xd/0xb): CET_U user save state byte size = 0x00000010 (16) CET_U user save state byte offset = 0x00000000 (0) supported in IA32_XSS or XCR0 = IA32_XSS (supervisor state) 64-byte alignment in compacted XSAVE = false XFD faulting supported = false CET_S supervisor features (0xd/0xc): CET_S supervisor save state byte size = 0x00000018 (24) CET_S supervisor save state byte offset = 0x00000000 (0) supported in IA32_XSS or XCR0 = IA32_XSS (supervisor state) 64-byte alignment in compacted XSAVE = false XFD faulting supported = false Quality of Service Monitoring Resource Type (0xf/0): Maximum range of RMID = 255 supports L3 cache QoS monitoring = true L3 Cache Quality of Service Monitoring (0xf/1): Conversion factor from IA32_QM_CTR to bytes = 64 Maximum range of RMID = 255 Counter width = 44 QoS monitoring counter size-24 = 0x14 (20) IA32_QM_CTR bit 61 is overflow = false (QoS monitoring counter size synth) = 44 supports L3 occupancy monitoring = true supports L3 total bandwidth monitoring = true supports L3 local bandwidth monitoring = true Resource Director Technology Allocation (0x10/0): L3 cache allocation technology supported = true L2 cache allocation technology supported = false memory bandwidth allocation supported = false L3 Cache Allocation Technology (0x10/1): length of capacity bit mask = 0x10 (16) Bit-granular map of isolation/contention = 0x00000000 infrequent updates of COS = false code and data prioritization supported = true highest COS number supported = 0xf (15) extended processor signature (0x80000001/eax): family/generation = 0xf (15) model = 0x1 (1) stepping id = 0x2 (2) extended family = 0xa (10) extended model = 0x6 (6) (family synth) = 0x19 (25) (model synth) = 0x61 (97) (simple synth) = AMD Ryzen (Raphael B2) [Zen 4], 5nm extended feature flags (0x80000001/edx): x87 FPU on chip = true virtual-8086 mode enhancement = true debugging extensions = true page size extensions = true time stamp counter = true RDMSR and WRMSR support = true physical address extensions = true machine check exception = true CMPXCHG8B inst. = true APIC on chip = true SYSCALL and SYSRET instructions = true memory type range registers = true global paging extension = true machine check architecture = true conditional move/compare instruction = true page attribute table = true page size extension = true multiprocessing capable = false no-execute page protection = true AMD multimedia instruction extensions = true MMX Technology = true FXSAVE/FXRSTOR = true SSE extensions = true 1-GB large page support = true RDTSCP = true long mode (AA-64) = true 3DNow! instruction extensions = false 3DNow! instructions = false extended brand id (0x80000001/ebx): raw = 0x10000000 (268435456) BrandId = 0x0 (0) PkgType = 0x1 (1) AMD feature flags (0x80000001/ecx): LAHF/SAHF supported in 64-bit mode = true CMP Legacy = true SVM: secure virtual machine = true extended APIC space = true AltMovCr8 = true LZCNT advanced bit manipulation = true SSE4A support = true misaligned SSE mode = true 3DNow! PREFETCH/PREFETCHW instructions = true OS visible workaround = true instruction based sampling = true XOP support = false SKINIT/STGI support = true watchdog timer support = true lightweight profiling support = false 4-operand FMA instruction = false TCE: translation cache extension = true NodeId MSR C001100C = false TBM support = false topology extensions = true core performance counter extensions = true NB/DF performance counter extensions = true data breakpoint extension = true performance time-stamp counter support = false LLC performance counter extensions = true MWAITX/MONITORX supported = true Address mask extension support = true brand = "AMD Ryzen 9 7945HX with Radeon Graphics " L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax): instruction # entries = 0x40 (64) instruction associativity = 0xff (255) data # entries = 0x48 (72) data associativity = 0xff (255) L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx): instruction # entries = 0x40 (64) instruction associativity = 0xff (255) data # entries = 0x48 (72) data associativity = 0xff (255) L1 data cache information (0x80000005/ecx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 0x8 (8) size (KB) = 0x20 (32) L1 instruction cache information (0x80000005/edx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 0x8 (8) size (KB) = 0x20 (32) L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax): instruction # entries = 0x200 (512) instruction associativity = 2-way (2) data # entries = 0xc00 (3072) data associativity = 6 to 7-way (5) L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx): instruction # entries = 0x200 (512) instruction associativity = 4 to 5-way (4) data # entries = 0xc00 (3072) data associativity = 8 to 15-way (6) L2 unified cache information (0x80000006/ecx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 8 to 15-way (6) size (KB) = 0x400 (1024) L3 cache information (0x80000006/edx): line size (bytes) = 0x40 (64) lines per tag = 0x1 (1) associativity = 0x9 (9) size (in 512KB units) = 0x80 (128) RAS Capability (0x80000007/ebx): MCA overflow recovery support = true SUCCOR support = true HWA: hardware assert support = false scalable MCA support = true Advanced Power Management Features (0x80000007/ecx): CmpUnitPwrSampleTimeRatio = 0x0 (0) Advanced Power Management Features (0x80000007/edx): TS: temperature sensing diode = true FID: frequency ID control = false VID: voltage ID control = false TTP: thermal trip = true TM: thermal monitor = true STC: software thermal control = false 100 MHz multiplier control = false hardware P-State control = true TscInvariant = true CPB: core performance boost = true read-only effective frequency interface = true processor feedback interface = false APM power reporting = false connected standby = true RAPL: running average power limit = true Physical Address and Linear Address Size (0x80000008/eax): maximum physical address bits = 0x30 (48) maximum linear (virtual) address bits = 0x30 (48) maximum guest physical address bits = 0x0 (0) Extended Feature Extensions ID (0x80000008/ebx): CLZERO instruction = true instructions retired count support = true always save/restore error pointers = true INVLPGB instruction = false RDPRU instruction = true memory bandwidth enforcement = true MCOMMIT instruction = false WBNOINVD instruction = true IBPB: indirect branch prediction barrier = true interruptible WBINVD, WBNOINVD = true IBRS: indirect branch restr speculation = true STIBP: 1 thr indirect branch predictor = true CPU prefers: IBRS always on = false CPU prefers: STIBP always on = true IBRS preferred over software solution = true IBRS provides same mode protection = true EFER[LMSLE] not supported = true INVLPGB supports TLB flush guest nested = false ppin processor id number supported = false SSBD: speculative store bypass disable = true virtualized SSBD = false SSBD fixed in hardware = false CPPC: collaborative processor perf ctrl = true PSFD: predictive store forward disable = true not vulnerable to branch type confusion = true branch sampling feature support = false (vuln to branch type confusion synth) = false Size Identifiers (0x80000008/ecx): number of threads = 0x20 (32) ApicIdCoreIdSize = 0x5 (5) performance time-stamp counter size = 40 bits (0) Feature Extended Size (0x80000008/edx): max page count for INVLPGB instruction = 0x0 (0) RDPRU instruction max input support = 0x1 (1) SVM Secure Virtual Machine (0x8000000a/eax): SvmRev: SVM revision = 0x1 (1) SVM Secure Virtual Machine (0x8000000a/edx): nested paging = true LBR virtualization = true SVM lock = true NRIP save = true MSR based TSC rate control = true VMCB clean bits support = true flush by ASID = true decode assists = true SSSE3/SSE5 opcode set disable = false pause intercept filter = true pause filter threshold = true AVIC: AMD virtual interrupt controller = true virtualized VMLOAD/VMSAVE = true virtualized global interrupt flag (GIF) = true GMET: guest mode execute trap = true X2AVIC: virtualized X2APIC = true supervisor shadow stack = true guest Spec_ctl support = true ROGPT: read-only guest page table = true host MCE override = true INVLPGB/TLBSYNC hyperv interc enable = false VNMI: NMI virtualization = true IBS virtualization = true guest SVME addr check = true NASID: number of address space identifiers = 0x8000 (32768): L1 TLB information: 1G pages (0x80000019/eax): instruction # entries = 0x40 (64) instruction associativity = full (15) data # entries = 0x48 (72) data associativity = full (15) L2 TLB information: 1G pages (0x80000019/ebx): instruction # entries = 0x0 (0) instruction associativity = L2 off (0) data # entries = 0x40 (64) data associativity = full (15) Performance Optimization Identifiers (0x8000001a/eax): 128-bit SSE executed full-width = false MOVU* better than MOVL*/MOVH* = true 256-bit SSE executed full-width = true Instruction Based Sampling Identifiers (0x8000001b/eax): IBS feature flags valid = true IBS fetch sampling = true IBS execution sampling = true read write of op counter = true op counting mode = true branch target address reporting = true IbsOpCurCnt and IbsOpMaxCnt extend 7 = true invalid RIP indication support = true fused branch micro-op indication support = true IBS fetch control extended MSR support = true IBS op data 4 MSR support = false IBS L3 miss filtering support = true Lightweight Profiling Capabilities: Availability (0x8000001c/eax): lightweight profiling = false LWPVAL instruction = false instruction retired event = false branch retired event = false DC miss event = false core clocks not halted event = false core reference clocks not halted event = false continuous mode sampling = false tsc in event record = false interrupt on threshold overflow = false Lightweight Profiling Capabilities: Supported (0x8000001c/edx): lightweight profiling = false LWPVAL instruction = false instruction retired event = false branch retired event = false DC miss event = false core clocks not halted event = false core reference clocks not halted event = false continuous mode sampling = false tsc in event record = false interrupt on threshold overflow = false Lightweight Profiling Capabilities (0x8000001c/ebx): LWPCB byte size = 0x0 (0) event record byte size = 0x0 (0) maximum EventId = 0x0 (0) EventInterval1 field offset = 0x0 (0) Lightweight Profiling Capabilities (0x8000001c/ecx): latency counter bit size = 0x0 (0) data cache miss address valid = false amount cache latency is rounded = 0x0 (0) LWP implementation version = 0x0 (0) event ring buffer size in records = 0x0 (0) branch prediction filtering = false IP filtering = false cache level filtering = false cache latency filteing = false Cache Properties (0x8000001d): --- cache 0 --- type = data (1) level = 0x1 (1) self-initializing = true fully associative = false extra cores sharing this cache = 0x1 (1) line size in bytes = 0x40 (64) physical line partitions = 0x1 (1) number of ways = 0x8 (8) number of sets = 64 write-back invalidate = false cache inclusive of lower levels = false (synth size) = 32768 (32 KB) --- cache 1 --- type = instruction (2) level = 0x1 (1) self-initializing = true fully associative = false extra cores sharing this cache = 0x1 (1) line size in bytes = 0x40 (64) physical line partitions = 0x1 (1) number of ways = 0x8 (8) number of sets = 64 write-back invalidate = false cache inclusive of lower levels = false (synth size) = 32768 (32 KB) --- cache 2 --- type = unified (3) level = 0x2 (2) self-initializing = true fully associative = false extra cores sharing this cache = 0x1 (1) line size in bytes = 0x40 (64) physical line partitions = 0x1 (1) number of ways = 0x8 (8) number of sets = 2048 write-back invalidate = false cache inclusive of lower levels = true (synth size) = 1048576 (1024 KB) --- cache 3 --- type = unified (3) level = 0x3 (3) self-initializing = true fully associative = false extra cores sharing this cache = 0xf (15) line size in bytes = 0x40 (64) physical line partitions = 0x1 (1) number of ways = 0x10 (16) number of sets = 32768 write-back invalidate = true cache inclusive of lower levels = false (synth size) = 33554432 (32 MB) extended APIC ID = 30 Core Identifiers (0x8000001e/ebx): core ID = 0xf (15) threads per core = 0x2 (2) Node Identifiers (0x8000001e/ecx): node ID = 0x0 (0) nodes per processor = 0x1 (1) AMD Secure Encryption (0x8000001f): SME: secure memory encryption support = true SEV: secure encrypted virtualize support = false VM page flush MSR support = false SEV-ES: SEV encrypted state support = false SEV-SNP: SEV secure nested paging = false VMPL: VM permission levels = false RMPQUERY instruction support = false VMPL supervisor shadow stack support = false Secure TSC supported = false virtual TSC_AUX supported = false hardware cache coher across enc domains = false SEV guest exec only from 64-bit host = false restricted injection = false alternate injection = false full debug state swap for SEV-ES guests = false disallowing IBS use by host = false VTE: SEV virtual transparent encryption = false VMGEXIT parameter support = false virtual TOM MSR support = false IBS virtual support for SEV-ES guests = false VMSA register protection support = false SMT protection support = false SVSM communication page MSR support = false VIRT_RMPUPDATE & VIRT_PSMASH MSR support = false encryption bit position in PTE = 0x33 (51) physical address space width reduction = 0x2 (2) number of VM permission levels = 0x0 (0) number of SEV-enabled guests supported = 0x0 (0) minimum SEV guest ASID = 0x0 (0) PQoS Enforcement (0x80000020): L3 external bandwidth = true L3 external slow memory bandwidth = true bandwidth monitoring event configuration = true L3 range reservation support = true PQoS Enforcement for L3 External Bandwidth (0x80000020/1): capacity bitmask length = 0xc (12) number of classes of service = 0xf (15) PQoS Enforcement for L3 External Slow Memory Bandwidth (0x80000020/2): capacity bitmask length = 0xc (12) number of classes of service = 0xf (15) PQoS Enforcement for Bandwidth Monitoring Event Configuration (0x80000020/3): number of bandwidth events available = 0x2 (2) reads to local NUMA = true reads to non-local NUMA = true non-temporal writes to local NUMA = true non-temporal writes to non-local NUMA = true reads to slow memory in local NUMA = true reads to slow memory in non-local NUMA = true dirty victims from QoS = true 0x80000020 0x04: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000 Extended Feature 2 (0x80000021): no nested data-breakpoints = true LFENCE always serializing = true SMM paging configuration lock support = true null selector clears base = true upper address ignore support = true automatic IBRS = true SMM_CTL MSR not supported = true prefetch control MSR support = true CPUID disable for non-privileged = true microcode patch size = 5568 (0x15c0) Extended Performance Monitoring and Debugging (0x80000022): AMD performance monitoring V2 = true AMD LBR V2 = true AMD LBR stack & PMC freezing = true number of core perf ctrs = 0x6 (6) number of LBR stack entries = 0x10 (16) number of avail Northbridge perf ctrs = 0x10 (16) Multi-Key Encrypted Memory Capabilities (0x80000023): secure host multi-key memory support = false number of encryption key IDs = 0x0 (0) 0x80000024 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000 0x80000025 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000 AMD Extended CPU Topology (0x80000026): extended APIC ID = 30 --- level 0 --- level number = 0x0 (0) level type = core (1) bit width of level = 0x1 (1) power efficiency ranking available = false cores heterogeneous at this level = false components have varying number of cores = false number of logical processors at level = 0x2 (2) 0x80000027 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000 0x80000028 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000 (instruction supported synth): CMPXCHG8B = true conditional move/compare = true PREFETCH/PREFETCHW = true (multi-processing synth) = multi-core (c=32) (multi-processing method) = AMD (APIC widths synth): CORE_width=4 SMT_width=1 (APIC synth): PKG_ID=0 CORE_ID=15 SMT_ID=0 (uarch synth) = AMD Zen 4, 5nm (synth) = AMD Ryzen (Raphael B2) [Zen 4], 5nm